FIGS. 1A to FIG. 1C are flow diagrams showing a conventional method of forming contact plugs.
Referring to FIG. 1A, a semiconductor substrate 10 is provided that has a cell array region "a" and a peripheral circuit region "b". Gate electrode layers 12 are formed in the cell array region "a". The gate electrode layers 12 includes polysilicon layer pattern 12a, a silicide layer pattern 12b, and an insulating spacer 12c, formed in that order over the semiconductor substrate 10. An interlayer insulating film 14 is then formed over the semiconductor substrate 10 including the gate electrode layers 12.
Note that the interlayer insulating film 14 has an uneven upper surface as it is deposited. In other words, because the interlayer insulating film 14 tends to be conformal, the upper surface of the interlayer insulating film 14 follows the contours producing by the underlaying structures formed on the semiconductors 10. This means that the position of the surface in the cell array region "a" and the peripheral circuit region "b" is very much different, causing a large step.
Referring to FIG. 1B, at least one contact hole 16 is opened through the interlayer insulating film 14 so as to expose an upper surface of the semiconductor substrate 10 proximate to the gate electrode layers 12. A conductive layer 18, for example a polysilicon layer is deposited over interlayer insulating film 14 to overfill the contact hole 16. The conductive layer 18 follows the topology produced by the underlaying insulating film layer 14.
Referring to FIG. 1C, the conductive layer 18, i.e., the polysilicon layer, and the interlayer insulating film 14 are both removed using a chemical-mechanical polishing (CMP) process in one step, thereby planarizing the interlayer insulating film 14 and forming a contact plug 20.
However, the above-mentioned CMP process must use slurries having no selectivity in the removal rate with respect to the polysilicon layer 18 and the interlayer insulating film 14, i.e., having the same removal rate, so as to remove simultaneously the polysilicon layer 18 and interlayer insulating film 14 through one step.
Thus, the conventional method mentioned above has many problems. The production of a slurry having the above-mentioned characteristics is difficult and controlling an end point of the CMP process is also difficult.
Furthermore, it is inevitable that the contact hole 16 is formed to have a deep depth. This is because the interlayer insulating film 14 of the cell array region "a" is formed very thickly so as to provide adequate margins for the CMP process.
In addition, one step of the CMP process used for removing a great deal of the interlayer insulating film 14 and the polysilicon layer 18 causes poor planarity and uniformity of the CMP layer.
Better margins for CMP process can be obtained by forming dummy gates in the peripheral circuit region "b" and planarizing the interlayer insulating film 14. However, the dummy gates affect the device, thus degrading electrical characteristics of the device.